With advances in the integrated circuit manufacturing technology, 3D memory devices with multiple planes of memory cells are provided to achieve greater storage capacity. Conventionally, when performing data erasing on a memory device, electron holes must be generated via gated-induce drain leakage (GIDL) currents at the string select line (SSL) or the ground select line (GSL) gate edge. However, minority carrier is generally slow and very sensitive to junction engineering and thus decreasing the data erase time.
Therefore, there is a need for a technology for improving the data erasing speed of 3D memory devices.